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| Philips Semiconductors Preliminary specification PowerMOS transistor Logic level FET PHX3055L GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic full-pack envelope. The device features high avalanche energy capability, stable blocking voltage, fast switching and high thermal cycling performance with low thermal resistance. Intended for use in Switched Mode Power Supplies (SMPS), motor control circuits and general purpose switching applications. QUICK REFERENCE DATA SYMBOL VDS ID Ptot RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Total power dissipation Drain-source on-state resistance MAX. 60 9.4 28 0.18 UNIT V A W PINNING - SOT186A PIN 1 2 3 gate drain source DESCRIPTION PIN CONFIGURATION case SYMBOL d g case isolated 123 s LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER ID IDM PD PD/Ths VGS VGSM EAS IAS Tj, Tstg Continuous drain current Pulsed drain current Total dissipation Linear derating factor Gate-source voltage Non-repetitive gate source voltage Single pulse avalanche energy Peak avalanche current Operating junction and storage temperature range CONDITIONS Ths = 25 C; VGS = 10 V Ths = 100 C; VGS = 10 V Ths = 25 C Ths = 25 C Ths > 25 C tp50s VDD 50 V; starting Tj = 25C; RGS = 50 ; VGS = 10 V VDD 50 V; starting Tj = 25C; RGS = 50 ; VGS = 10 V MIN. - 55 MAX. 9.4 5.9 26 28 0.22 15 20 25 6 150 UNIT A A A W W/K V V mJ A C ISOLATION LIMITING VALUE & CHARACTERISTIC Ths = 25 C unless otherwise specified SYMBOL Visol PARAMETER R.M.S. isolation voltage from all three terminals to external heatsink CONDITIONS f = 50-60 Hz; sinusoidal waveform; R.H. 65% ; clean and dustfree MIN. TYP. MAX. 2500 UNIT V Cisol Capacitance from T2 to external f = 1 MHz heatsink - 10 - pF October 1997 1 Rev 1.000 Philips Semiconductors Preliminary specification PowerMOS transistor Logic level FET PHX3055L THERMAL RESISTANCES SYMBOL Rth j-hs Rth j-a PARAMETER Thermal resistance junction to heat sink. Thermal resistance junction to ambient CONDITIONS MIN. TYP. 55 MAX. 4.5 UNIT K/W K/W ELECTRICAL CHARACTERISTICS Tj = 25 C unless otherwise specified SYMBOL V(BR)DSS V(BR)DSS / Tj RDS(ON) VGS(TO) gfs IDSS IGSS Qg(tot) Qgs Qgd td(on) tr td(off) tf Ld Ls Ciss Coss Crss PARAMETER Drain-source breakdown voltage Drain-source breakdown voltage temperature coefficient Drain-source on resistance Gate threshold voltage Forward transconductance Drain-source leakage current Gate-source leakage current Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance CONDITIONS VGS = 0 V; ID = 0.25 mA VDS = VGS; ID = 0.25 mA VGS = 10 V; ID = 6 A VDS = VGS; ID = 0.25 mA VDS = 50 V; ID = 6 A VDS = 60 V; VGS = 0 V VDS = 48 V; VGS = 0 V; Tj = 150 C VGS = 30 V; VDS = 0 V ID = 10 A; VDD = 48 V; VGS = 10 V VDD = 30 V; ID = 10 A; RG = 24 ; RD = 2.7 MIN. 60 1.0 3.5 TYP. 0.06 0.13 1.5 5.5 0.1 1 10 7.5 1.9 5.5 12 105 26 35 4.5 7.5 290 103 40 MAX. 0.18 2.0 25 250 100 10 3 7 UNIT V V/K V S A A nA nC nC nC ns ns ns ns nH nH pF pF pF Measured from drain lead 6 mm from package to centre of die Measured from source lead 6 mm from package to source bond pad VGS = 0 V; VDS = 25 V; f = 1 MHz SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS Ths = 25 C unless otherwise specified SYMBOL IS ISM VSD trr Qrr PARAMETER Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IS = 10 A; VGS = 0 V IS = 10 A; VGS = 0 V; dI/dt = 100 A/s TYP. 40 0.1 MAX. 9.4 48 1.5 UNIT A A V ns C October 1997 2 Rev 1.000 Philips Semiconductors Preliminary specification PowerMOS transistor Logic level FET PHX3055L 120 110 100 90 80 70 60 50 40 30 20 10 0 PD% Normalised Power Derating with heatsink compound 10 Zth(j-hs) Transient Thermal Impedance (K/W) PHX3055E 0.5 1 0.2 0.1 0.05 0.1 0.02 P D 0.01 0 tp D= tp T t T 0 20 40 60 80 Ths / C 100 120 140 0.001 1us 10us 100us 1ms 10ms tp, pulse width (s) 0.1s 1s 10s Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Ths) ID% Normalised Current Derating with heatsink compound Fig.4. Transient thermal impedance. Zth j-hs = f(t); parameter D = tp/T PHP3055E Tj = 25 C 7V 6.5 V 10 6V 5.5 V 5 5V VGS = 4.5 V 120 110 100 90 80 70 60 50 40 30 20 10 0 15 ID, Drain current (Amps) 10 V 0 20 40 60 80 Ths / C 100 120 140 0 0 5 10 15 20 VDS, Drain-Source voltage (Volts) 25 30 Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Ths); conditions: VGS 10 V ID, Drain current (Amps) 100 Fig.5. Typical output characteristics. ID = f(VDS); parameter VGS 0.4 V )= DS /ID tp = 10 us RDS(on), Drain-Source on resistance (Ohms) 5.5 V 6V 6.5 V 7V PHP3055E 10 RD O S( N 0.3 100 us 1 ms DC 1 10 ms 100 ms 0.2 10 V 0.1 VGS = 15 V Tj = 25 C 0.1 0 1 10 100 VDS, Drain-source voltage (Volts) 1000 0 5 10 ID, Drain current (Amps) 15 20 Fig.3. Safe operating area. Ths = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp Fig.6. Typical on-state resistance. RDS(ON) = f(ID); parameter VGS October 1997 3 Rev 1.000 Philips Semiconductors Preliminary specification PowerMOS transistor Logic level FET PHX3055L 15 ID, Drain current (Amps) VDS = 30 V PHP3055E Tj = 25 C Tj = 175 C 4 VGS(TO) / V max. 10 3 typ. min. 2 5 1 0 0 0 2 4 6 VGS, Gate-source voltage (Volts) 8 10 -60 -40 -20 0 20 40 60 Tj / C 80 100 120 140 Fig.7. Typical transfer characteristics. ID = f(VGS); parameter Tj PHP3055E Tj = 25 C 3 Tj = 175 C Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 0.25 mA; VDS = VGS ID / A SUB-THRESHOLD CONDUCTION 4 gfs, Transconductance (S) VDD = 30 V 1E-01 1E-02 1E-03 2% typ 98 % 2 1E-04 1 1E-05 0 1E-06 0 5 10 ID, Drain current (Amps) 15 0 1 2 VGS / V 3 4 Fig.8. Typical transconductance. gfs = f(ID); parameter Tj a Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS Ciss, Coss, Crss, Junction capacitances (pF) PHP3055E Normalised RDS(ON) = f(Tj) 1000 1.5 Ciss Coss 1.0 100 Crss 0.5 0 -60 -40 -20 0 20 40 60 Tj / C 80 100 120 140 10 1 10 VDS, Drain-source voltage (Volts) 100 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 C = f(Tj); ID = 10 A; VGS = 10 V Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz October 1997 4 Rev 1.000 Philips Semiconductors Preliminary specification PowerMOS transistor Logic level FET PHX3055L 15 VGS, Gate-Source voltage (Volts) ID = 10 A Tj = 25 C PHP3055E 20 IF, Source-drain diode current (Amps) VGS = 0 V PHP3055E VDS = 30 V 48 V 15 10 Tj = 175 C Tj = 25 C 10 5 5 0 0 5 10 Qg, Gate charge (nC) 15 0 0 0.5 1 VSDS, Source-drain voltage (Volts) 1.5 Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); parameter VDS Switching times (ns) VDD = 30 V VGS = 10 V RD = 2.7 Ohms ID = 10 A Tj = 25 C tr td(off) tf td(on) PHP3055E Fig.16. Source-Drain diode characteristic. IF = f(VSDS); parameter Tj EAS, Normalised unclamped inductive energy (%) 1000 120 110 100 90 80 70 60 50 40 30 20 10 100 10 1 0 20 40 60 RG, Gate resistance (Ohms) 80 100 0 20 40 60 80 100 Starting Tj ( C) 120 140 Fig.14. Typical switching times. td(on), tr, td(off), tf = f(RG) Normalised Drain-source breakdown voltage V(BR)DSS @ Tj V(BR)DSS @ 25 C Fig.17. Normalised unclamped inductive energy. EAS% = f(Tj) 1.15 1.1 1.05 1 0.95 0.9 + L VDS VGS 0 RGS T.U.T. R 01 shunt VDD -ID/100 0.85 -100 -50 0 50 Tj, Junction temperature (C) 100 150 Fig.15. Normalised drain-source breakdown voltage. V(BR)DSS/V(BR)DSS 25 C = f(Tj) Fig.18. Unclamped inductive test circuit. 2 EAS = 0.5 LID V(BR)DSS /(V(BR)DSS - VDD ) October 1997 5 Rev 1.000 Philips Semiconductors Preliminary specification PowerMOS transistor Logic level FET PHX3055L MECHANICAL DATA Dimensions in mm Net Mass: 2 g 10.3 max 3.2 3.0 4.6 max 2.9 max Recesses (2x) 2.5 0.8 max. depth 2.8 6.4 15.8 19 max. max. seating plane 15.8 max 3 max. not tinned 3 2.5 13.5 min. 1 0.4 M 2 3 1.0 (2x) 0.6 2.54 0.5 2.5 1.3 0.9 0.7 5.08 Fig.19. SOT186A; The seating plane is electrically isolated from all terminals. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for F-pack envelopes. 3. Epoxy meets UL94 V0 at 1/8". October 1997 6 Rev 1.000 Philips Semiconductors Preliminary specification PowerMOS transistor Logic level FET PHX3055L DEFINITIONS Data sheet status Objective specification Product specification Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1997 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. October 1997 7 Rev 1.000 |
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